### Lecture 4: Logic Design -- Fan-in; Simulating Combinational Circuits

(discuss full adder, decoder, propagation delays from lecture 3 notes)

#### Fan-in (note: not covered in text)

• sum-of-products form suggests any combinatorial function can be computed in 3 gate delays (one delay for inverters, one for ANDs, one for OR)
• but gates are limited in their fan-in (number of inputs a gate has)
• so, for example, if fan-in is f, it takes log (base f) n gate delays to OR or AND together n inputs

#### Simulating Combinational circuits

• importance of simulating designs before they are built
• tooling up to build a new VLSI circuit is very expensive
(low cost is obtained by making a large number of a single design)
• hard to debug a circuit once it is built
• distributing a chip (processor) with a bug can cause huge problems
• special purpose simulators ... operate from logic diagrams
• alternative: write programs (in C, Fortran, Pascal, ...) which mimic the operation of circuits

#### Principles of writing programs to simulate circuits

• each signal variable represents one signal (wire): has value 0 or 1
• expressions which compute these signal variables use only Boolean operations
(in C, & [AND], | [inclusive OR], ^ [exclusive OR], and ~ [NOT])
• no conditional assignment: each variable is always assigned the same Boolean function of inputs and other variables
• single assignment: each variable is only assigned a value once in the process of computing a set of output values (no cycles in the combinational circuit)
• busses (sets of signal wires) represented by arrays
• examples: full-adder.c, 4-bit-adder.c