V22.0436 - Prof. Grishman

Lecture 17: MIPS Processor Design: Single Cycle Control (cont'd)

Text: Section 5.3

Single cycle control logic (see also Lecture 12 notes)

How the single cycle CPU works

Sequence reflects data flow ... everything happens in a single clock cycle.

for all instructions: fetch instruction from instruction memory

for R-type instructions:

for load:

for store:

for beq: