V22.0436 - Prof. Grishman

Practice Final Exam Questions (2)

IO

  1. Consider a handshaking circuit for asynchronous data transmission, where the transmitter sets and resets a DATA READY signal, and the receiver sets and resets an ACKNOWLEDGE signal. Why must the receiver wait for ACKNOWLEDGE to be reset to 0 before commencing the transmission of the next bit? Indicate what could go wrong if it didnít.

Combinational Circuits

  1. Design a fast circuit to compute the sum of two 2-bit positive numbers. Construct a truth table for such a circuit, and then convert the truth table into a sum-of-products logic formula for each output. What is the propagation delay of this circuit, from input to output?

Sequential Circuits

  1. Design a 2-bit down counter with a RESET input. If RESET=0, the counter counts down by 1 modulo 4) on the next clock cycle; if RESET=1, the counter resets to 0 on the next clock cycle. Draw the state transition diagram; provide the transition table for this circuit; and design the circuit using D-type master-slave FFs and standard gates (AND, OR, NAND, NOR, inverters).
  2. Given D-type master-slave FFs, AND, OR, NAND, NOR gates, inverters, and multiplexers, design a 4-word, 2 bit per word register file with a single input port and a single output port.

MIPS Processor Design

  1. What is the purpose of the ìsign extendî circuit in the MIPS CPU you simulated? Suppose we didnít have a sign extend circuit; what limitation would there be on branch instructions?
  2. Is it possible for a program to modify its instructions in the single cycle MIPS CPU? in the multi-cycle CPU?