Do text problems 7.1, 7.2, 7.3, 7.4, and 7.8
Also, suppose that we have a processor where the CPI without cache misses is 1.2, that the instruction miss rate is 2%, the data fetch miss rate is 4%, and one half of the instructions contain a data fetch. Suppose the cache miss penalty is 7 cycles. What is the CPI if cache misses are taken into account?
Due December 8. Late assignments are penalized 10% for each weekday late.