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CSCI-UA.0436 - Prof. Grishman

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Lecture 7 - MIPS instruction set and MIPS ALU

#### MIPS assembly language

- labels at beginning of line, followed by a colon (:)
- comments begin with #

- registers referred to in assembly language as $0 ... $31, or
by
names
indicating typical uses, such as $s0 ... $s7

- use of register 0 ($zero) as constant 0
- assembler directives for data: .word; .byte; .asciiz (zero-terminated
ASCII
string)
- data segment preceded by
`.data`; code segment
preceded by `.text`

- pseudoinstructions for common sequences
- MIPS hardware only provides branch on equal / branch on not
equal / set if less than

- other conditional branches can be implemented as
two-instruction sequences
- MIPS assembler provides many of these as pseudoinstructions
- These use $1 for intermediate results

####
MIPS Simulator

Several assembler / simulator systems have been developed for MIPS.

The original one, SPIM, can be downloaded from the SPIM
web site, http://www.cs.wisc.edu/~larus/spim.html

The
simulator is described in Appendix B, section B-9

An alternative Java-based MIPS IDE, MARS, is available at
http://courses.missouristate.edu/KenVollmar/MARS/

#### Using the MIPS Core Instruction Set (sections 2.1 to 2.7 + 2.10)

- Basic: load and store; add, add immediate,
subtract,
and, or

- Dealing with constants ...small constants and large constants
- LUI (load upper immediate) operation

- Dealing with large addresses using LUI operation
- handled automatically by assembler

- Branch: unconditional; branch on
equal/unequal;
testing for less than/greater than
- Array addressing: load and store instructions compute
effective address (register + constant)

#### MIPS ALU (text, Appendix C.5)

An ALU (arithmetic-logical unit) is a combinational circuit capable
of
computing a variety of arithmetic and logical functions.
- operations needed for MIPS core instruction set: add,
subtract,
and, or, nor, zero test, comparison

- general strategy: different circuits combined by multiplexer;
multiplexer
select becomes function select for ALU (Fig. C..5.6)

- inverting B input for subtraction (Fig. C.5.8)
- inverting A (as well as B) lets us get NOR using AND gates
(Fig.
C.5.9)

- feed output of high-order bit of adder to low-order bit for
"set
on
less"
operation (Fig. C.5.11)

- use OR gate on ALU output for "equal" test (Fig. C.5.12)

####
Carry look-ahead: introduction (text, Appendix C.6)

- simplest adder is "ripple carry": slow (delay time linear in
size
of
operands)
- add time is usually critical in determining overall cycle time
of
a
machine
- can speed up addition by introducing notion of "carry
generate"
and
"carry
propagate"