CSCI-UA.0436 - Prof. Grishman

Lecture 23:  Bus structure of a modern PC

A hierarchy of busses

The single ISA bus of the original PC has evolved into a hierarchy of busses, consisting of very fast CPU busses connecting to fast local busses connecting to (relatively) slow external busses

Typical older machine organization
    CPU
    north bridge (memory controller hub)
       connects to RAM and AGP
    south bridge (I/O controller hub)
       connects to all other I/O

Connection from CPU to north bridge is system bus
    also referred to as front-side bus (FSB)
    [in contrast to back side bus, used on some machines to connect CPU to an L2 or L3 cache]

north and south bridges


AMD 64-bit chips and Intel Core i7 chips moved the memory controller onto the CPU, part of a trend towards greater consolidation.
When the memory controller moves onto the CPU, the FSB is replaced by a QuickPath Interconnect (QPI) [Intel] or HyperTransport [AMD] to the IO Hub (former Southbridge).

Most recent chips (AMD Fusion, Intel Sandy Bridge -- introduced 2011) consolidate all north bridge functions into CPU.

Local Ports and Busses

AGP
    accelerated graphics port (dedicated port -- not a bus)
    introduced when transfer speed of PCI bus was no longer sufficient for graphics devices
    basic bus is 32 bits, 66 MHz clock, so initially 266 MB/sec, but later versions were X2, X4, X8 speed;  X8 = 2.1 GB/sec
    now largely replaced by PCIe (PCI Express) bus

PCI bus
    Peripheral Component Interconnect bus
    Introduced in 1993 as 32-bit bus, 33 MHz (raised withh PIC 2.2 to 66 MHz)
    Replaced ISA and EISA busses as primary bus for faster devices;  ISA remains as a device on PCI bus
    Upgrade in 1998:  PCI-X, PCI Extended, 64-bit bus, 133 MHz

Upgrade in 2004:  PCIe, PCI Express
    PCIe is not a real bus, but a set of serial point-to-point interconnections (same software interface as PCI)
    Each 'lane' of PICe supports 250MB/sec (full duplex)
        in 2007, PCIe 2.0, 500MB/sec
        in late 2010, PCIe 3.0, doubles PCIe 2.0 speed
    Can support up to 32 lanes (can connect multiple lanes to same device for faster speeds)

Busses for connecting I/O Devices

General tendency towards serial links to avoid problems of signal skew as frequencies increase

For disk drives
    ATA (Advanced Technology Attachment) ... 16-bit parallel bus introduced in 1980's for PC disks
    now replaced by
    SATA (Serial ATA) ... serial bus (not a shared bus) ... initially 1.5Gb/s, then 3.0Gb/s, with 6.0Gb/s introduced in 2009

USB
    Universal Serial Bus
    Introduced 1996
    Three speeds:  low (1.5 Mbps), full (12 Mbps), and (with USB 2.0 in 2000) hi (480 Mbps)
        A new, faster standard (USB 3.0 -- 4.8 Gbps) was released in August 2008 with product introductions in 2011 (Dell) and 2012 (Apple)
    4 wires (differential data wires + power and ground)  (8 wires for USB 3.0)