CSCI-UA.0436 - Prof. Grishman

Lecture 13: MIPS Processor Design: Data Paths and Control Logic

[presentation by Prof. Gottlieb  see his notes]

Text: Section 4.3- 4.4

Combining data paths

We have seen the data paths needed for the individual types of instructions. To construct a complete data path for our machine, we combine these data paths, using multiplexers where necessary (Fig. 4.11).

Data paths and control

These data paths require various control signals: register numbers, read/write control for memories and registers, function for ALU, select lines for registers. The values of these control signals must be determined based on the instruction being executed.

The instructions we are considering (lw, sw, beq, add, sub, and, or, slt) are stored in three instruction formats (Fig. 4.14). The opcode of the instruction is stored in the high 6 bits (bits 26 to 31). However, the R-type instructions all are assigned opcode 0, and are differentiated by the "function" field, bits 0 to 5 of the instruction.

The register numbers are stored in the same place in all these instructions, and so we can connect the instruction fields (the output of the instruction memory) directly to the register number inputs on the register file. We need one multiplexer, however, since the number of the register to write sometimes appears in the rd field, bits 11 to 15 (for R-type instructions) and sometimes in the rt field, bits 16 to 20 (for load instructions). This produces the circuit shown in Fig. 4.15.