CSCI-UA.0436 - Prof. Grishman
Assignment 6: MIPS Control Unit
In this assignment you will use Logisim to build two separate
the main control and the ALU control for the single-cycle MIPS
processor covered in
class and described in chapter 4. The hardware
designs are shown in Appendix D.
The ALU control should have as inputs (from top to bottom) a
bundle, ALUOp, and a 6-wire bundle, Func. Its output
be a 4-wire bundle, ALUcon.
The main control unit should have as input the opcode, a 6-bit
Op. The outputs should be (from top to bottom): branch,
RegDst, MemRead, MemToReg, ALUOp, MemWrite, ALUSrc, and RegWrite.
is a 2-wire bundle; the rest are all single wires.
For extra credit, add the
logic for the nor instruction
ALU control. Note that the logic in the book is carefully
optimized for the selected instructions, so adding nor may require some
redesign of the circuit, not just adding gates. For the extra
credit, it is not required that the design be as optimized as the
Due Wednesday, November 14th.
Mail your homework (the .circ file) to email@example.com and firstname.lastname@example.org and mark
the mail CompArch -- Asgn 6.
have included the extra credit, say so in the mail.