V22.0436 - Computer Architecture - Fall 2010 - Prof. Grishman

Course Schedule
links will be filled in as lectures are presented
Class Date Topic Text Assignment
(date assigned)
1 Sept. 7
Intro; time & frequency; history
Chap. 1


Logic Design Appendix C

2 Sept. 9
Gates and circuits;  canonical form
C.2, C.3

3 Sept. 14
Simulation;  propagation delay

#1 (gates / universality)
4 Sept. 16
Sequential circuits
C.7, C.8
5 Sept. 21
FFs; Synchronous circuits and memory elements
C.9 #2 (comparator)
6 Sept. 23
Finite-state machines
C.10


MIPS and its ALU
Chap. 2

7
Sept. 28 MIPS instruction set
Chap. 2
#3 (register file)
8 Sept. 30
MIPS instructions and MIPS ALU
Chap. 2; C.5

9 Oct. 5
carry look-ahead
C.6
#4 (MIPS program)
10 Oct. 7
arithmetic Chap. 3*



Processor Design Chap. 4
11 Oct. 12
Building a data path 4.1 - 4.3
#5 (ALU)
12 Oct. 14
Data paths/single cycle control
(review for mid-term)
4.3, 4.4

13 Oct. 19
Mid-term

14 Oct. 21
(go over mid-term) Performance 1.4, 1.7

15 Oct. 26
Performance and Pipelining
1.4, 1.7, 4.5
#6 (control unit)
16 Oct. 28
Pipelining
4.6*, 4.7*, 4.8*

17 Nov. 2
Multiple instruction issue
4.10

18 Nov. 4
Processor limits and multithreading
7.1-7.3, 7.5
#7 (CPU)
19 Nov. 9
Multi-thread programs




Memory
Chap. 5

20 Nov. 11
Memory Technology and Introduction to Cache 5.1

21 Nov. 16
Cache organization 5.2

22 Nov. 18
Cache:  blocks, writes, performance 5.3



Input-output
Chap. 6

23 Nov. 23
types of devices 6.1 - 6.4

24 Nov. 30
buses and I/O transfer 6.5 - 6.6
#8 (cache)
25 Dec. 2
Bus structure of modern PCs 6.5 - 6.6
#9 (multithreading)


Parallelism
Chap. 7

26 Dec. 7
Multiprocessors
7.1 - 7.3, 7.5

27 Dec. 9
Multiprocessors and clusters
7.3, 7.4

28
Dec. 14
review for final exam

* partial coverage
 
Final Exam: Thursday, December 23, 4pm - 5:50pm, Room 312 Warren Weaver