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V22.0436 - Prof. Grishman

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Lecture 5: Logic Design -- Synchronous Circuits

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Timing for synchronous circuits (text, section C.7)

- basic requirement: delay of combinational circuit to compute next
state
< clock period

#### Representing sequential circuits (text, sec. C.10)

- a sequential circuit can be described as a
*finite state
machine*

- state machine includes a next-state function and an output
function

(text, figure C.10.1)
- we will consider a simple version where the output is just part
of the current state

- next-state function can be represented by a graph or a table
- graph: finite state transition network
- transition table: table which gives new state as a function of
current
state and inputs

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Finite state transition network

- a network consists of a set of nodes connected by arcs
- each node represents a state of the circuit (so a circuit with n
bits
of
registers may have 2
^{n} states)
- each arc represents a possible transition between states; it is
labeled
by the condition (if any) under which the transition is made

#####
Transition table

In a transition table, the input columns represent the state of the
circuit
and the inputs to the circuit; the output columns represent the next
state
of the circuit.
##### Designing a sequential circuit

- (sometimes) draw a transition network for the circuit
- build a transition table
- use the transition table as the truth table for the "next state"
combinatorial
circuit
- convert this table to a circuit
- if necessary, build an output function truth table and convert it
to a
circuit
- example: binary up-counter; binary up-down counter
- example: "traffic light" circuit from text

#### Register files (text, pp. C-53 and C-54)

- minimal register file has data input, data output, register
number, and
write signal
- general arithmetic operation takes two operands (from registers)
and produces a result (to be stored inn a register); to
accomodate this

- can provide separate read and write register numbers
- can provide multiple read ports

- selecting a register to read is controlled by a multiplexer
(figure C.8.8)
- selecting a register to write is controlled by a decoder (figure
C.8.9)
- figures from Prof. Gottlieb's notes: register file | read
ports | write port