### Lecture 4: Logic Design -- Sequential Circuits:  Latches and Flip-Flops

(text, sections C.7 and C.8)

#### Combinational vs. sequential circuits

• in a combinational circuit, output (after some delay) is a function of inputs
• in contrast, a sequential circuit holds state information: the output is a function of the state of the device, as well as its inputs; in other words, sequential circuits have memory

#### Simple latches

• RS latch (reset-set latch): set and reset inputs (text, figure C.8.1)
• D-type latch: clock and data inputs (text, figure C.8.2): use of clock to control when a latch is updated
• register: set of latches with a common clock

#### Synchronous circuits

• consists of a set of registers controlled by a common clock, along with a combinatorial circuit to compute the next state (text, section C.7)
• up-counter as simple example of synchronous circuit
• race problem if same latches are used for input to and output from combinatorial circuit (figure C.7.3)
• use of edge-triggered registers to address race problem

#### Master-slave flip-flops

• provide an way of implementing edge-triggered FFs
• built from two simple flip-flops (latches) with complementary clocks (figure C.8.4)
• changes output on falling edge