V22.0436 - Prof. Grishman

Lecture 17: Multiple Issue:  SIMD, EPIC, and superscalar

Pipelining takes advantage of instruction-level parallelism ... the ability to execute more than one instruction at a time.

Some machines now try to go beyond pipelining to execute more than one instruction at a clock cycle, producing an effective CPI < 1. This is possible if we duplicate some of the functional parts of the processor (e.g., have two ALUs or a register file with 4 read ports and 2 write ports), and have logic to issue several instructions concurrently.  There are two general approaches to multiple issue:  static multiple issue (where the scheduling is done at compile time) and dynamic multiple issue (where the scheduling is done at execution time), also known as superscalar.   Intel Core 2 processors are superscalar and can issue up to 4 instructions per clock cycle.

Static Multiple Issue

Dynamic Multiple Issue (superscalar)

Intel superscalar architectures