V22.0436 - Prof. Grishman
Assignment 5: MIPS ALU
In this assignment you will use Logisim to build the MIPS ALU,
including all of the inputs and outputs shown in figure C.5.12 except for the Overflow
output. There will be two 32-bit inputs, A and B; two 1-bit
inputs, Ainvert and Bnegate; and a 2-bit input, Operation.
There will be one 32-bit output, Result, and one 1-bit output, Zero.
Rather than build a 1-bit ALU and then combine 32 of them, you will
probably find it easier to build the ALU directly from 32-bit-wide
components. By setting the "bit width" attribute to 32 for the
AND gate, you get in effect 32 AND gates. Similarly you can
32-bit-wide OR gate, inverter, multiplexers, and adder (the adder is
part of the arithmetic library).
Most of the wires will therefore be 32-bit bundles. The only
instances where you have to split out individual wires involve the slt logic (where you have to
get the high bit of the adder output and connect it to the low bit of a
input) and the zero logic (where you have to OR together all 32
wires). You may find it easier to first build the zero logic (a
32-input NOR gate) as a separate sub-circuit which has one input (a
32-bit bundle) and one output (zero).
Due Tuesday, October 26th.
Mail your homework (the .circ file) to firstname.lastname@example.org and email@example.com and mark
the mail CompArch -- Asgn 5.