V22.0436 - Computer Architecture - Fall 2009 - Prof. Grishman

Course Schedule
links will be filled in as lectures are presented
Class Date Topic Text Assignment
(date assigned)
1 Sept. 8
Intro; time & frequency; history
Chap. 1


Logic Design Appendix C

2 Sept. 10
Gates and circuits;  canonical form
C.2, C.3

3 Sept. 15
Simulation;  propagation delay

#1 (gates / universality)
4 Sept. 17
Sequential circuits
C.7, C.8
5 Sept. 22
FFs; Synchronous circuits and memory elements
C.9 #2 (comparator)
6 Sept. 24
Finite-state machines
C.10
7
MIPS and its ALU
Chap. 2

7
Sept. 29 MIPS instruction set
Chap. 2
#3 (register file)
8 Oct. 1
MIPS instructions and MIPS ALU
Chap. 2; C.5

9 Oct. 6
carry look-ahead
C.6
#4 (MIPS program)
10 Oct. 8
arithmetic Chap. 3*

11 Oct. 13
Mid-term

12 Oct. 15
(go over mid-term)
#5 (ALU)


Processor Design
Chap. 4

13 Oct. 20
Building a data path 4.1 - 4.3

14 Oct. 22
Data paths/single cycle control
4.3
15 Oct. 27
Single cycle control 4..4
16 Oct. 29
Measuring performance 1.4, 1.7
#6 (control unit)
17 Nov. 3
Pipelining
4.5, 4.6*

18 Nov. 5
Pipelining:  Hazards
4.7*, 4.8*

19 Nov. 10
Advanced Instruction-level Parallelism
4.10
#7 (CPU)


Memory
Chap. 5

20 Nov. 12
Memory Technology and Introduction to Cache 5.1

21 Nov. 17
Cache organization 5.2

22 Nov. 19
Cache:  blocks, writes, performance 5.3



Input-output
Chap. 6

23 Nov. 24
types of devices 6.1 - 6.4

24 Dec. 1
buses and I/O transfer 6.5 - 6.6
#8 (cache)
25 Dec. 3
Bus structure of modern PCs 6.5 - 6.6



Parallelism
Chap. 7

26 Dec. 8
Multicores, multithreading, and multiprocessors
7.1 - 7.3, 7.5

27 Dec. 10
Multiprocessors and clusters
7.3, 7.4

28
Dec. 15
review for final exam

* partial coverage
 
Final Exam: Thursday  Dec. 17, 2009, 4:00-5:50 PM, 201 Warren Weaver Hall (not in regular classroom)