V22.0436 - Computer Architecture - Fall 2008 - Prof. Grishman

Course Schedule
links will be filled in as lectures are presented
Class Date Topic Text Assignment
1 Sept. 2
Intro; time & frequency; history
Chap. 1


Logic Design Appendix B
2 Sept. 4
Gates and circuits;  canonical form
B.2, B.3

3 Sept. 9
Simulation;  propagation delay

#1 (gates / universality)
4 Sept. 11
Sequential circuits
B.7, B.8
5 Sept. 16
FFs; Synchronous circuits and memory elements
B.9 #2 (comparator)
6 Sept. 18
Finite-state machines
B.10
7
MIPS and its ALU


7
Sept. 23 MIPS instruction set
Chap. 2
#3 (register file)
8 Sept. 25
MIPS instructions and MIPS ALU
Chap. 2; B.5

9 Sept. 30
carry look-ahead
B.6
#4 (MIPS program)
10 Oct. 2
Mid-term

11 Oct. 7
(go over mid-term)

12 Oct. 9
arithmetic
Chap. 3*



Processor Design
Chap. 5

13 Oct. 16
Building a data path 5.3
#5 (ALU)
14 Oct. 21
Data paths/single cycle control
5.3
15 Oct. 23
Single cycle control 5.4


Performance Issues and Cache


16 Oct. 28
Measuring performance Chap. 4* #6 (control unit)
17 Oct. 30
Multiple cycle control
5.5

18 Nov. 4
Pipelining
Chap. 6*
19 Nov. 6
Current trends in high performance processors 6.9 #7 (CPU)
20 Nov. 11
Discussion of Assignment #7


21 Nov. 13
Memory Technology and Introduction to Cache 7.1-7.2

22 Nov. 18
Cache organization
7.3

23 Nov. 20
Cache:  blocks, writes, performance


24 Nov. 25 Two-level cache;  cache performance

#8 (cache)


Input-output Chap. 8
25 Dec. 2
types of devices 8.1, 8.2
26 Dec. 4
buses 8.4
27 Dec. 9
interrupts and DMA 8.5
28
Dec. 11
review for final exam

* partial coverage
 
Final Exam:  Tuesday, December 16th, 2:00 to 3:50 PM in 101 Warren Weaver