V22.0436 - Prof. Grishman
Practice Final Exam Questions
- A processor runs at 2GHz. What is the length of its clock cycle?
your answer in microseconds, nanoseconds, or picoseconds.)
- A disk has an access time of 10 ms. Assuming the time for data
is negligible, how many disk accesses can be performed each second?
- A disk rotates at 6000 RPM. What is its average rotational
- The access time of a disk is composed of ______________ and
- Suppose we have a loop of 10 machine instructions and we execute
this loop one billion times on a 2 GHz machine with a CPI of 2.0.
How long will the billion iterations of the loop take?
- Design a fast circuit to compute the sum of two 2-bit positive
Construct a truth table for such a circuit, and then convert the truth
table into a sum-of-products logic formula for each output. What is the
propagation delay of this circuit, from input to output?
- Given D-type master-slave or edge-triggered FFs, AND, OR, NAND,
NOR gates, inverters, and
multiplexers, design a 4-word, 2 bit per word register file with a
input port and a single output port.
MIPS Processor Design
- Write a MIPS program with a loop which copies the 20 words (80
at byte 1000 to the 20 words beginning at byte 2000.
- What is the purpose of the 'sign extend' circuit in the MIPS CPU
Suppose we didn't have a sign extend circuit; what limitation would
be on branch instructions?
- Is it possible for a program to modify its instructions in the
MIPS CPU? in the multi-cycle CPU?
Processor Performance and Pipelining
- Suppose that when program Zippo runs, it executes 200,000 loads,
stores, 699,998 R-type instructions, and 2 multiply instructions.
2 machine designs: in design M1, the clock rate is 1.5GHz; loads and
take 2 cycles, R-type instructions take 1 cycle, and multiplies take 5
cycles. In design M2, the clock rate is 1.0GHz and all instructions
1 cycle. Which machine is faster?
- On a pipelined MIPS machine, the instruction sequence
add $4, $2, $3
is an example of what type of hazard? We can use
______________________ to avoid stalling for this type of hazard.
- Consider two alternative caches, each of which has a capacity of
and a block size of one word. Cache D is a direct mapped cache, and
T is a two-way set associative cache. Suppose the cache is initially
and we fetch the words at the following addresses in sequence: 1, 2, 9,
3, 1, 5, 9. Which of these fetches will result in cache hits?
- Suppose that we have a 10 ns cache (it takes 10 ns to access the
identify a miss), and a memory system with a 100 ns access time. What
the average memory access time if the cache hit rate is 97%? If we
a larger cache, with a 12 ns access time but a hit rate of 98%, would
average memory access time increase or decrease?
- Suppose we have a floppy disk which transfers 50 KB and
CPU each time a byte is available. The CPU executes approximately 50
and the interrupt routine takes 25 instructions to transfer a byte to
What fraction of the CPU time will be occupied doing IO with the floppy
- Consider a handshaking circuit for asynchronous data
the transmitter sets and resets a DATA READY signal, and the receiver
and resets an ACKNOWLEDGE signal. Why must the receiver wait for
to be reset to 0 before commencing the transmission of the next bit?
what could go wrong if it didn't.
Exam: Tuesday, December 16th, 2:00 to 3:50 PM in 101
Warren Weaver. Open book,