2. Suppose that we have a processor where the CPI without cache
is 1.2, that the instruction miss rate is 2%, the data fetch miss rate
is 4%, and one half of the instructions contain a data fetch. Suppose
cache miss penalty is 15 cycles. What is the CPI if cache misses are
For extra credit: Look up the (L2) cache size of your own
CPU. Confirm that information by running the 'timer' program
(Lecture 24) for array sizes slightly smaller and larger than the cache
size and recording the increase in running time. (Report in a
small table the values of ARRAYSIZE, ITERATIONS, and the running
time.) For best effect, run the program with maximum optimization
Due December 9th.
Mail your homework (plain text or Word file) to email@example.com and to firstname.lastname@example.org (Mr. Yu-shun Cheng) and mark the mail CompArch -- Asgn 8. If you have included the extra credit, say so in the mail. You may also hand in a hard copy in class, although electronic submission is preferred.