V22.0436 - Prof. Grishman

Assignment 3:   Register File

In this assignment you will use Logisim to create a small register file, consisting of four 3-bit registers.  To build this register file, you may use basic gates (AND, OR, XOR, NOT, NAND, NOR, and XNOR gates) and registers as provided by Logisim.  To make the task easier, you will begin by building two subcircuits, a 4-way multiplexer and a 4-way decoder.

1.  Build a 4-way multiplexer.  Using Logisim, construct a device (from AND, OR, XOR, NOT, NAND, NOR, and XNOR gates) which has four data inputs, two select inputs, and a single output.  From top to bottom, the inputs to the multiplexer (on the left) will be select0, select1, data0, data1, data2, and data3.  If [select1  select0] are interpreted as a binary number n, then the data output should be equal to datan

2.  Build a 4-way decoder.  Using Logisim, construct a device (from AND, OR, XOR, NOT, NAND, NOR, and XNOR gates) which has two select inputs, and four data outputs.  From top to bottom, the inputs to the decoder (on the left) will be select0 and select1;  the outputs (on the right) will be out0, out1, out2, and out3.  If  [select1  select0] are interpreted as a binary number n, then outn = 1 and the other out signals should be 0.

Using registers and wire bundles:
In Logisim, click on "Project>Load Library>Load Built-in Library and then choose "Memory".  You will see, on the left-hand side of the window, a new folder of devices called "Memory".  Expand this folder by clicking on the "+" next to it.  You'll see a bunch of memory devices, including "Register".  When you click on Register you'll see a table open up at the bottom left, withh options for configuring the register.  The field you'll have to change is "Bit Width", which you should set to 3.

Once you place a register in the canvas section of Logisim (the big area where you create circuits), you'll see that it has three inputs, "D" (the3-bit data input) on the left, the clock/write-enable input on the bottom (it looks like a "^"), and a "clr" input next to it (this clears the register, but you won't need it for this assignment).  The only output is Q (3 bits).

To try out this register, create a 3-bit input pin (click on the input-pin icon on the top menu, and then change the "bit width" in the table at the bottom-left to "3") and connect it to the D input of the register.  This automatically creates a 3-wire "bundle".  Connect a 1-bit input pin to the write-enable line of the register.  Finally, connect the Q output of the register to a 3-bit output pin (click on the output-pin icon on the top menu, then select a bit width of 3).  Now you can experiment by changing the value of the 3-bit input and the value of the write-enable line to see how the output changes.

Note that, unlike the description in the text, the Logisim memory devices change state on the rising edge of the clock (i.e., when the clock/write-enable line goes up).  This does not affect your circuit design at all.

Next, try using a splitter to separate out the 3 wires in the bundle.  The splitter splits a multi-wire bundle into its individual wires, so that you can make separate connections to each wire.  Open the "Base" folder, click on "Splitter, and then chose the "Fan Out" and "Bit Width In" to be 3.
Connect the left (bundled) end of the splitter to the Q output of the register (deleting the 3-bit output pin you had before).  Connect each of the individual wires of the splitter to a 1-bit output pin.

3.  Build a 4-register register file, where each register has 3 bits.  The file should have one input port and one output port, both controlled by a common set of select lines. Use one of your decoders to control the write enable lines, as shown in Figure B.8.9, and 3 of your multiplexers to feed data out.  The final circuit should have the following inputs:  select0 and select1; write-enable;  and data-in (a 3 bit line).  It should have three outputs, data-out0, data-out1, and data-out2.  (Note:  this circuit will have a lot of connecting wires;  plan your layout and leave plenty of space between the components so you don't run out of room.)

Due in one week: September 30th.

Mail your homework (the .circ file) to  grishman@cs.nyu.edu and mark the mail CompArch -- Asgn 3.