V22.0436 - Prof. Grishman

Assignment 7:   MIPS Single-Cycle Processor

Using Logisim, build a complete single-clock-cycle-per-instruction MIPS processor as described in section ... of the text.

1.  Download the zip file CA Devices.zip, which contains  contains the circuits for a Register File, Instruction Memory, and Data Memory ;  unzip this file into a folder that you create just for this assignment.  These devices were originally built by Prof. Goldberg and have been slightly modified for this semester (to use a different clocking discipline).

2.  Into the same folder that you unzipped “CA Devices.zip”, put a copy of the file (with a .circ extension) containing the ALU that you built and of the file containing the Control circuits you built.

3. Run Logisim and load the libraries you need

When you start Logisim, you will need to load the following libraries:

Plexers, Arithmetic, and Memory (only for “register”, not “RAM”): Click “Project>Load Library>Built-in Library…”

CA devices: Click “Project>Load Library>Logisim Library…” and specify the file “CA device.circ” in the folder into which you unzipped “CA Devices.zip”.

ALU, Control: Click ““Project>Load Library>Logisim Library…” and specify the file containing your ALU and Control circuits.

4.  Construct the simple single-cycle MIPS processor described in section 5.4 of the text (Figure 5.17), using the register file, instruction memory, and data memory devices provided.  You may want to create additional subcircuits, such as for the sign extension and shift 2, to keep your main circuit manageable.  The provided register file and data memory use the master clock of Logisim;  you need to connect the PC to the master clock.

5.  After you have built the processor, test it on individual instructions by initializiing one word of data memory and one word of instruction memory.  We will later distribute some small programs which will be used to test the machine.

Due Wednesday, December 6th.

You should aim to have your machine working on individual instructions by Wednesday, November 29th, allowing the final week to getting it to run on full programs.

To test on full programs, follow the iinstructions prepared by Prof. Goldberg, using the test programs and data available as progmem.zip.  The test programs will only work with the latest version of Logisim, ver. 2.1.5 from Nov. 28, 2006.  Earlier versions of Logisim will report an error when trying to load the program files.

Mail your homework (the .circ file) to  grishman@cs.nyu.edu and to mgp255@nyu.edu (Ms. Merim Puthuparampil) and mark the mail CompArch -- Asgn 7.

The devices in the “CA devices” library

The illustrations below indicate the inputs and outputs of the three devices (Register File, Instruction Memory, Data Memory) found in the “CA devices” library.

Register File
write enable

read sel0 (5 bits)

read data0 (32 bits)
read sel1 (5 bits)


write sel (5 bits)

read data1 (32 bits)
write data (32 bits)






Instruction Memory


address (32 bits)
                 
output (32 bits)       




Data Memory
write enable

address (32 bits)

     output (32 bits)
write data (32 bits)



read enable


The register file and data memory both use the master clock, and load data one gate delay after the rise of the master clock.  They require that the 'write enable' control line be stable before the master clock falls.  Instruction and data memory are configured for 256 words of 32 bits;  the low 2 bits and high 22 bits of the address are ignored.