V22.0436 - Prof. Grishman
Assignment 4 - MIPS Assembly Language
Write a MIPS program, using a loop, which computes the sum of five
(32-bit) words in memory and stores the result in a word labeled sum.
Declare and initialize this array as part of your program. Verify
the operation of your code using the SPIM assembler/simulator.
Reminder: MIPS uses byte addressing, so the addresses of successive
words differ by 4, not 1.
Due in two weeks: October 18th.
Mail your homework (the assembly language program file) to firstname.lastname@example.org and to email@example.com (Ms. Merim
Puthuparampil) and mark
the mail CompArch -- Asgn 4.
SPIM Assembler Notes
The simulator is on the CD and can also be downloaded from the SPIM
web site, http://www.cs.wisc.edu/~larus/spim.html
You may use either numeric register identifiers ($1, $2, $3, ...) or
symbolic register identifiers ($s1, $s2, $s3, ...). If you use
numeric identifiers, do not
use $1; it is used by the assembler to expand instructions
involving 32-bit constants into two MIPS instructions.
Precede the instruction portion of your program with the assembler
Precede the data portion of your program with
the assembler directive ".data".
Label the first instruction you want executed "main:". The kernel
code will transfer there with a jal
(jump and link) instruction.
Finish your program with a "jr $ra"
instruction; this will return
to the kernel, which will then terminate execution.
So the basic structure of a program (to add 3 and 4) would be
Although the basic idea for this course is to program 'close to the
machine', the assembler in fact does lots of things which allow the
programmer to ignore constraints in the actual hardware, such as
aa: .word 3
bb: .word 4
cc: .word 0
main: lw $2, aa
lw $3, bb
add $4, $2, $3
sw $4, cc
Appendix A gives much more information about the assembler.
- loads and stores with addresses outside the allowed range for
address constants are expanded to 2-instruction sequences
- arithmetic with constants outside the allowed range for constants
are expanded to 2 or 3-instruction sequences
- pseudoinstructions are provided for the conditional branches not
provided in the hardware, including blt (branch on less than), ble (branch on less than or
equal), bgt (branch on
greater than), bge
(branch on greater than or equal)
- a load address (la)
$2, aa puts the address of aa into register $2
- a load immediate (li)
$2, 10 puts the constant 10 into register $2