Computer Systems Org I - Prof. Grishman

Lecture 27 - Dec. 8, 2005

Computer logic (P&P chapter 3), cont'd

Storage Element (P&P 3.4 - 5), cont'd

A register file is a small memory (P&P 3.5), which uses multiplexers to select the data to be read from the memory.  The register number inputs (address inputs) are used to control the multiplexers.  Two-port register files can read out two registers at the same time.

Large memory chips (RAM) use a conceptually similar design, but with much larger arrays of memory cells, and are significantly slower (tens of ns).

Building a processor (P&P chapter 4)

The data path of the processor consists primarily of an ALU and a register file.  This design, with a two-port register file, naturally supports register to register operations as on the LC-3.

A control unit gets as input the instruction and sets the various control lines (ALU select lines, register numbers, etc.). (P&P Fig. 4.3).

The CPU operates as a synchronous machine controlled by a clock (P&P 3.6).  This machines goes through a sequence of states to read the instruction and perform the specified operation.  Registers are updated only when the clock strikes.

Circuit and Processor speed

The speed of an individual gate -- how fast it can turn on or off -- is determined by the geometry and physical properties of the gate.  In general, smaller gates switch faster.

The propagation delay of a circuit is determined by the longest path through the circuit (slow vs. fast adders).

The 'clock rate' of a chip is the rate at which the clock strikes (e.g., 2 GHz).  The clock period is 1/clock rate (e.g., 0.5 ns).

How fast can we run the clock?  When the clock strikes, new data is loaded into the registers and the outputs of the registers change.  The changed values then have to propagate through the circuits of the machine until they reach the input of the next set of registers.  We shouldn't strike the clock again until the signals have time to reach the register inputs;  otherwise the values loaded into the inputs may be incorrect.  So the minimum clock period = the (maximum) propagation delay of the circuit, from register output to register input.