2. (P&P exercise 3.16, slightly modified) Given the following truth table for a 3-input even-parity circuit, write the sum-of-products Boolean formula for Z, and draw the gate-level logic circuit.

A |
B |
C |
Z |

0 |
0 |
0 |
1 |

0 |
0 |
1 |
0 |

0 |
1 |
0 |
0 |

0 |
1 |
1 |
1 |

1 |
0 |
0 |
0 |

1 |
0 |
1 |
1 |

1 |
1 |
0 |
1 |

1 |
1 |
1 |
0 |

3. (P&P execise 3.22, slightly modified) Implement a 4-to-1 multiplexer (figure 3.13) using (only) three 2-to-1 multiplexers (figure 3.12). Draw the resulting circuit, using the symbol for a 2-to-1 multiplexer, figure 3.12 (c). The circuit will have four data inputs, A, B, C, and D, two select inputs, S

4. Write the truth table for the following circuit.

Write your answers on one or more sheets of paper, staple the sheets together, and hand the sheet(s) in at the last class, December 13th. The assignment is worth 4 points, with 1/2 point penalty for each weekday late. If you are unable to submit the assignment in class on Dec. 13th, place it in my mailbox (715 Bway, 7th floor) and send a confirming email to grishman@cs.nyu.edu (if you can enter the diagrams electronically, you can submit the homework to grishman@cs.nyu.edu as an email).